The present invention relates generally to digital circuits and more particularly to a scan flip-flop.
Digital circuits play an important role in a variety of devices. System on Chip (SOC) devices, for example, are becoming more complex and the requirement to meet high performance and low power targets for such complex devices presents an ever-increasing challenge.
Flip-flops are among the basic building blocks used in digital circuits. Flip-flops are used in sequential circuits to store state information. State transitions occur at predetermined times, typically defined by rising or falling edges of a clock signal. A typical flip-flop has a data input, a clock input and a data output. Data at the data input is sampled, and provided at the output, at a rising or falling clock edge. Typically, flip-flops require the sampled input signal to remain stable after the clock edge for a defined duration. This duration is called the hold-time. If the input signal changes before the required minimum duration following the sampling clock edge, a hold-time violation occurs. A typical application where hold-time violations may be observed is in the testing of integrated circuits, LBIST (Logic built-in self-test) procedures, for example.
One known self-test procedure uses a scan test where many flip-flops in the circuit are connected together to effectively form a large shift register. A multiplexer at an input of a flip-flop is set to select either a scan test input during testing, or an ordinary data input during normal operation. A circuit block including a multiplexer and a flip-flop, with the multiplexer having a scan input, a normal data input, and an output interconnected to the input of a flip-flop, is called a scan flip-flop or scan cell. During scan tests, the combinatorial blocks in a circuit may be bypassed as scan test data is shifted into pipeline stages made of scan flip-flops. Scan flip-flops so operated have no combinational logic connected between them and signals propagate from one stage to another very quickly, potentially causing hold-time violations. To counter hold-time violations, buffers are often inserted between scan flip-flops. However, this has the disadvantage of requiring additional silicon area and its associated cost.
Typically, when in test mode (or scan mode), scan test patterns are shifted (or scanned) into flip-flops, the circuit is put into normal mode for one or more cycles, then placed in scan mode again and the contents of the scan registers (test results) are serially shifted out (or scanned out) for comparison with expected output values. The random nature of this test procedure, i.e., the random shifting of data through scan chains causes high switching activity due to the high level of toggling in the LBIST design. Consequently, during such a test procedure, there is high peak and average power consumption. Initial peak power values are a particular concern because the LBIST design moves from a low activity to a very high activity state in a short span of time. If power consumption exceeds certain limits, then shifted data may be corrupted. One known way of reducing power consumption during shift mode involves reducing the shift (clock) frequency. However this has the disadvantage of increasing the test runtime.
Therefore it would be advantageous to provide a scan flip-flop that consumes less power during shift mode without sacrificing performance during a self-test or resistance to hold violations.